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ICM7562/7542/7522
ICmic
IC MICROSYSTEMS
12/10/8-Bit Low Power Dual DACs With Serial Interface and Voltage Output
FEATURES * 12/10/8-Bit Dual DAC in 08 Lead MSOP Package * Ultra-Low Power Consumption * Guaranteed Monotonic * Wide Output Voltage Swing * Three-wire SPI/QSP and Microwire Interface Compatible * Three Software-Selectable Power-Down Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) * Schmitt-Triggered Inputs for Direct Interfacing to Opto-couplers APPLICATION * Battery-Powered Applications * Industrial Process Control * Digital Gain and Offset Adjustment BLOCK DIAGRAM
OVERVIEW The ICM7562, ICM7542 and ICM7522 are 12-Bit, 10-Bit and 8-Bit Voltage Output, Low Power, Dual DACs respectively, with guaranteed monotonic behavior. These DACs are available in 08 Lead MSOP package. They have three Software-Selectable Power-Down Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional safety feature for applications that drive transducers or valves. The operating supply range is 2.7V to 5.5V. The input interface is an easy to use three-wire SPI, QSPI and Microwire compatible interface. The DAC has SchmittTriggered Inputs for Direct Interfacing to Opto-couplers easily.
REFIN
ICM7562/7542/7522
INPUT REGISTER A DAC REGISTER A
x2
VOA
DAC A
RESISTOR NETWORK A
x2
INPUT REGISTER B DAC REGISTER B
DAC B
RESISTOR NETWORK B
VOB
INPUT CONTROL LOGIC, REGISTERS AND LATCHES
POWER DOWN CONTROL
CS
SDI
SCK
Rev. A6
ICmic reserves the right to change specifications without prior notice
ICM7562/7542/7522
PACKAGE
08 Lead MSOP VDD GND CS SCK 1 2 3 4 TOP VIEW 8 7 6 5 VOB VOA REFIN SDI
PIN DESCRIPTION (8 Lead MSOP)
Pin 1 2 3 4 5 6 7 8
Name VDD GND CS SCK SDI REFIN VOA VOB
I/O I I I I I I O O Supply Voltage Ground Active Low Chip Select (CMOS) Serial Clock Input (CMOS) Serial Data Input (CMOS) Reference Voltage Input to DAC A-B DAC A Output Voltage DAC B Output Voltage
Description
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Rev. A6
ICmic reserves the right to change specifications without prior notice
ICM7562/7542/7522
ABSOLUTE MAXIMUM RATINGS Symbol VDD IIN VIN_ VIN_REF TSTG TSOL Parameter Supply Voltage Input Current Digital Input Voltage (SCK, SDI , CLR , CS ) Reference Input Voltage Storage Temperature Soldering Temperature Value -0.3 to 7.0 +/- 25.0 -0.3 to 7.0 -0.3 to 7.0 -65 to +150 300 Unit V mA V V
oC oC
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
ORDERING INFORMATION Part ICM7562 ICM7542 ICM7522 DC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Operating Temperature Range -40 oC to 85 oC -40 oC -40 oC to to 85 oC 85 oC
Package 08-Lead MSOP 08-Lead MSOP 08-Lead MSOP
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
DC PERFORMANCE ICM7562 N DNL INL ICM7542 N DNL INL ICM7522 N DNL INL GE OE VDD IDD Resolution Differential Nonlinearity Integral Nonlinearity Gain Error Offset Error Supply Voltage Supply Current Full Scale at VDD=5..5 Full Scale at VDD=3.6 2.7 5 125 100 (Notes 1 & 3) (Notes 1 & 3) 8 0.05 0.25 +1.0 +0.75 +0.5 +25 5.5 200 190 Bits LSB LSB % of FS mV V A A Resolution Differential Nonlinearity Integral Nonlinearity (Notes 1 & 3) (Notes 1 & 3) 10 0.1 1.0 +1.0 +3.0 Bits LSB LSB Resolution Differential Nonlinearity Integral Nonlinearity (Notes 1 & 3) (Notes 1 & 3) 12 0.4 4.0 +1.0 +12.0 Bits LSB LSB
STATIC ACCURACY
POWER REQUIREMENTS
Rev. A6
ICmic reserves the right to change specifications without prior notice
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ICM7562/7542/7522
DC ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OUTPUT CHARACTERISTICS Vout VOSC Rout Output Voltage Range Short Circuit Current Output Impedance Output Line Regulation LOGIC INPUTS VIH VIL Digital Input High Digital Input Low Digital Input Leakage AC ELECTRICAL CHARACTERISTICS
(VDD = 2.7V to 5.5V, VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted)
(Note 3) Power-Down at 1 K Ohm Power-Down at 100 K Ohm VDD=2.7 V to 5.5 V (Note 2) (Note 2)
0 60 0.9 90 -3.0 2.4 1 100 0.4
VDD 150 1.1 110 3.0
V mA K K mV/V V
0.8 5
V
Symbol SR
Parameter Slew Rate Settling Time Mid-scale Transition Glitch Energy
Test Conditions
Min
Typ 2 8 40
Max
Unit V/ s s nV-S
Note 1: Note 2: Note 3:
Linearity is defined from code 110 to 3990 (ICM7562) Linearity is defined from code 16 to 1023 (ICM7542) Linearity is defined from code 4 to 255 (ICM7522) Guaranteed by design; not tested in production See Applications Information
TIMING CHARACTERISTICS
(VDD = 2.7V to 5.5V, all specifications TMIN to TMAX unless otherwise noted)
Symbol t1 t2 t3 t4 t5 t6
Parameter SCK Cycle Time Data Setup Time Data Hold Time CS Rising Edge CS Falling Edge to SCK Rising Edge SCK Falling edge to CS Pulse Width
Test Conditions (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2)
Min 30 10 10 0 15 20
Typ
Max
Unit ns ns ns ns ns ns
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Rev. A6
ICmic reserves the right to change specifications without prior notice
ICM7562/7542/7522
SERIAL INTERFACE TIMING AND OPERATION DIAGRAM
t5
t1
t4
t6
CS
SCK
SDI
C3 t2 t3 MSB
C2
C1
D0
LSB
Figure 1. Serial Interface Timing Diagram
CS
(ENABLE SCK)
(UPDATE OUTPUT)
SCK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB
LSB
Figure 2. Serial Interface Operation Diagram
CONTENTS OF INPUT SHIFT REGISTER DEVICE BIT CONTROL WORD MSB ICM7562 ICM7542 ICM7522 12 10 8 C3 C3 C3 C2 C2 C2 C1 C1 C1 C0 C0 C0 D11 D10 D9 D7 D8 D6 D9 D7 D5 D8 D6 D4 D7 D5 D3 D6 D4 D2 D5 D3 D1 D4 D2 D0 D3 D1 A3 D2 D0 A2 D1 A1 A1 DATA WORD LSB D0 A0 A0
Figure 3. Contents of Input Shift Register
Rev. A6
ICmic reserves the right to change specifications without prior notice
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ICM7562/7542/7522
C3 C2 C1 C0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1
DATA (D11~D0) (D9~D0) (D7~D0) Data Data Data Data Data Data Data Data Data Data
DAC A B A B A B All All All All
FUNCTION Input Register transparent, data shifted to DAC register directly, VOA updated Input Register transparent, data shifted to DAC register directly, VOB updated Data Shifted to Input Register, VOA unchanged Data Shifted to Input Register, VOB unchanged Data Shifted from Input Register to DAC register, VOA updated Data Shifted from Input Register to DAC register, VOB updated Input Registers transparent, data shifted to DAC register directly, All VOUT updated Data Shifted to Input Registers, All VOUT unchanged Data Shifted from Input Registers to DAC registers, All VOUT updated Please see Power Down Mode Control Table Table 1. Serial Interface Input Word
CONTROL C3 C2 C1 C0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D11~D5 D9~D3 D7~D1 X X X X X X X X X X X X D4 D2 D0 0 0 0 0 0 0 0 0 1 1 1 1 D3 D1 A3 X X X X X X X X X X X X
DATA D2 D0 A2 0 0 0 0 1 1 1 1 0 0 0 0 D1 A1 A1 0 0 1 1 0 0 1 1 0 0 1 1 D0 (7562) A0 (7542) A0 (7522) 0 1 0 1 0 1 0 1 0 1 0 1
DAC
FUNCTION
A A A A B B B B All All All All
DAC O/P, wakeup Floating Output Output is terminated with 1K Output is terminated with100 K DAC O/P, wakeup Floating Output Output is terminated with 1K Output is terminated with100 K DAC O/P, wakeup Floating Output Output is terminated with 1K Output is terminated with100 K
Table 2. Power Down Mode Control
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Rev. A6
ICmic reserves the right to change specifications without prior notice
ICM7562/7542/7522
DETAILED DESCRIPTION The ICM7562 is a 12-bit voltage output Dual DAC. The ICM7542 is the 10-bit version of this family and the ICM7522 is the 8-bit version. These devices have a 16-bit data-in shift register and each DAC has a double buffered input. This family of DACs has a guaranteed monotonic behavior. The operating supply range is from 2.7V to 5.5V. Reference Input The reference input accepts positive DC and AC signals. The voltage at REFIN sets the full-scale output voltage of both the DACs. The reference input voltage range is from 0 to VDD-1.5V. The impedance at this pin is very high (greater than 10 M Ohm). Each DACs output amplifier is configured in a gain of 2 configuration. This means that the full-scale output of each DAC will be 2x VREF. To determine the output voltage for any code, use the following equation. VOUT = 2 x (VREF x (D / (2n))) Where D is the numeric value of DAC's decimal input code, VREF is the reference voltage and n is number of bits, i.e. 12 for ICM7562, 10 for ICM7542 and 8 for ICM7522. Output Buffer Amplifier The Dual DAC has 2 output amplifiers connected in a gain of 2 configuration. These amplifiers have a wide output voltage swing. The actual swing of the output amplifiers will be limited by offset error and gain error. See the Applications Information section for a more detailed discussion. The output amplifier can drive a load of 2.0 K to VDD or GND in parallel with a 500 pF load capacitance. The output amplifier has a full-scale typical settling time of 8 s and it dissipates about 100 A with a 3V supply voltage. Serial Interface and Input Logic This dual DAC family uses a standard 3-wire connection compatible with SPI/QSPI and Microwire interfaces. Data is always loaded in 16-bit words which consist of 4 address and control bits (MSBs) followed by 12 bits (see Figure .3). The last 5 bits of this 12 bit word are also used for power down control (see tables 1 and 2). Each DAC is double buffered with an input latch and DAC latch. Serial Data Input SDI (Serial Data Input) pin is the data input pin for all DACs. Data is clocked in on the falling edge of SCK which has a Schmitt trigger internally to allow for noise immunity on the SCK pin. This specially eases the use for opto-coupled interfaces. The Chip Select pin which is the 3rd pin of 8 lead MSOP package is active low. This pin frames the input data for Rev. A6
synchronous loading and must be low when data is being clocked into the part. There is an onboard counter on the clock input and after the 16th clock pulse the data is automatically transferred to a 16-bit input latch and the 4 bit control word (C3~C0) is then decoded and the appropriate DAC is updated or loaded depending on the control word (see Table 1). Chip Select pin must be pulled high (level-triggered) and back low for the next data word to be loaded in. This pin also disables the SCK pin internally when pulled high. The DAC has a double-buffered input with an input latch and a DAC latch. The DAC output will swing to its new value when data is loaded into the DAC latch. The user has three options: loading only the input latch, updating the DAC with data previously loaded into the input latch or loading the input latch and updating the DAC at the same time with a new code. The actual data that gets loaded into the DAC latch is D11~D0 for the ICM7562, D9~D0 for the ICM7542 and D7~D0 for the ICM 7522.
Power-Down Mode The DAC have three Software-Selectable Power-Down Output Impedances (1 K Ohm, 100 K Ohm and Hi-Z) as additional safety feature for applications that drive transducers or valves. The power down can be done with loading the control word with 1111 (C0 to C3). Tthe selection of the Output Impedance of DAC is controlled by the last 5 bits. See Table 1 and Table 2 for details of operation of this function. Power-On Reset There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage output will go to ground. APPLICATIONS INFORMATION Power Supply Bypassing and Layout Considerations As in any precision circuit, careful consideration has to be given to layout of the supply and ground. The return path from the GND to the supply ground should be short with low impedance. Using a ground plane would be ideal. The supply should have some bypassing on it. A 10 F tantalum capacitor in parallel with a 0.1 F ceramic with a low ESR can be used. Ideally these would be placed as close as possible to the device. Avoid crossing digital and analog signals, specially the reference, or running them close to each other. Output Swing Limitations The ideal rail-to-rail DAC would swing from GND to VDD. However, offset and gain error limit this ability. Figure 4 illustrates how a negative offset error will affect the output. The output will limit close to ground since this is single supply part, resulting in a dead-band area. As a larger input is loaded into the DAC the output will eventually rise above ground. This is why the linearity is specified for a starting code greater than zero.
ICmic reserves the right to change specifications without prior notice
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ICM7562/7542/7522
Figure 5 illustrates how a gain error or positive offset error will affect the output when it is close to VDD. A positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a dead-band of codes close to full-scale.
VDD
OFFSET AND GAIN ERROR
DEADBAND DEADBAND
NEGATIVE OFFSET
POSITIVE OFFSET
Figure 4. Effect of Negative Offset
Figure 5. Effect of Gain Error and Positive Offset
8
Rev. A6
ICmic reserves the right to change specifications without prior notice
ICM7562/7542/7522
PACKAGE INFORMATION 8 Lead MSOP
Rev. A6
ICmic reserves the right to change specifications without prior notice
9
ICM7562/7542/7522
ORDERING INFORMATION
ICM75X2 P G
G = RoHS Compliant Lead-Free package. Blank = Standard package. Non lead-free. Package M = 8-Lead MSOP
Device 6 - ICM7562 4 - ICM7542 2 - ICM7522
10
Rev. A6
ICmic reserves the right to change specifications without prior notice

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